R5F100GC datasheet(161/202 Pages) RENESAS

161 / 202 page

RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

C)

Page 161 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock

input)

(TA =

40 to +105C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

HS (high-speed main) Mode

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

24 MHz < fMCK

28/fMCK

20 MHz < fMCK

 24 MHz

24/fMCK

8 MHz < fMCK

 20 MHz

20/fMCK

4 MHz < fMCK

 8 MHz

16/fMCK

4.0 V

 EVDD0  5.5

2.7 V

 Vb  4.0 V

fMCK

 4 MHz

12/fMCK

24 MHz < fMCK

40/fMCK

20 MHz < fMCK

 24 MHz

32/fMCK

16 MHz < fMCK

 20 MHz

28/fMCK

8 MHz < fMCK

 16 MHz

24/fMCK

4 MHz < fMCK

 8 MHz

16/fMCK

2.7 V

 EVDD0 < 4.0

2.3 V

 Vb  2.7 V

fMCK

 4 MHz

12/fMCK

24 MHz < fMCK

96/fMCK

20 MHz < fMCK

 24 MHz

72/fMCK

16 MHz < fMCK

 20 MHz

64/fMCK

8 MHz < fMCK

 16 MHz

52/fMCK

4 MHz < fMCK

 8 MHz

32/fMCK

SCKp cycle time

Note 1

tKCY2

2.4 V

 EVDD0 < 3.3

1.6 V

 Vb  2.0 V

fMCK

 4 MHz

20/fMCK

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V

tKCY2/2

 24

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V

tKCY2/2

 36

SCKp high-/low-level

width

tKH2,

tKL2

2.4 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 2

tKCY2/2

 100

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V

1/fMCK + 40

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V

1/fMCK + 40

SIp setup time

(to SCKp

) Note2

tSIK2

2.4 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V

1/fMCK + 60

SIp hold time

(from SCKp

) Note 3

tKSI2

1/fMCK + 62

4.0 V

 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



2/fMCK + 240

2.7 V

 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



2/fMCK + 428

Delay time from SCKp



to SOp output

Note 4

tKSO2

2.4 V

 EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V

Cb = 30 pF, Rb = 5.5 k



2/fMCK + 1146

(Notes, Caution and Remarks are listed on the next page.)

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