TSV6391 datasheet(6/22 Pages) STMICROELECTRONICS

6 / 22 page

Electrical characteristics

TSV6390, TSV6390A, TSV6391, TSV6391A

6/22

DocID17118 Rev 2

Table 5: VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, RL connected to VCC/2

(unless otherwise specified)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

DC performance

Vio

Offset voltage

TSV6390 and TSV6391

TSV6390A and TSV6391A

0.5

Tmin < Top < Tmax,

TSV6390 and TSV6391

4.5

Tmin < Top < Tmax,

TSV6390A and TSV6391A

ΔVio/ΔT

Input offset voltage drift

μV/°C

Iio

Input offset current

(1)

Tmin < Top < Tmax

100

Iib

Input bias current

(1)

Tmin < Top < Tmax

100

CMR

Common mode rejection ratio

20 log (ΔVic/ΔVio)

0 V to 3.3 V, Vout = 1.65 V

Tmin < Top < Tmax

Avd

Large signal voltage gain

RL = 10 kΩ, Vout = 0.5 V to 2.8 V

Tmin < Top < Tmax

VOH

High-level output voltage

RL = 10 kΩ

Tmin. < Top < Tmax

VOL

Low-level output voltage

RL = 10 kΩ

Tmin < Top < Tmax

Iout

Isink

Vout = 3.3 V

Tmin < Top < Tmax

Isource

Vout = 0 V

Tmin < Top < Tmax

ICC

Supply current,

SHDN = VCC

No load, Vout = VCC/2

µA

Tmin < Top < Tmax

AC performance

GBP

Gain bandwidth product

RL = 10 kΩ, CL = 100 pF

2.2

MHz

Gain

Minimum gain for stability

Phase margin = 60°, Rf = 10 kΩ,

RL = 10 kΩ, CL = 20 pF,

V/V

-3

Slew rate

RL = 10 kΩ, CL = 100 pF,

Vout = 0.5 V to 2.8 V

0.9

V/μs

Equivalent input noise voltage

f = 1 kHz

nV/√Hz

Notes:

(1)

Guaranteed by design.

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