S5D9 datasheet(64/115 Pages) RENESAS

64 / 115 page

R01DS0303EU0100 Rev.1.00

Page 64 of 115

Nov 3, 2016

S5D9

2. Electrical Characteristics

Figure 2.40

SCI input/output timing in clock synchronous mode

Table 2.23

SCI timing (2)

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.

For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.

Item

Symbol

Min

Max

Unit

Test

conditions

Simple

SPI

SCK clock cycle output

(master)

tSPcyc

4 (PCLKA ≤ 60 MHz)

8 (PCLKA > 60 MHz)

65536

tPcyc

Figure 2.41

SCK clock cycle input (slave) -

6 (PCLKA ≤ 60 MHz)

12 (PCLKA > 60 MHz)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall time

tSPCKr, tSPCKf

-20

Data input setup time

tSU

33.3

Figure 2.42 to

Figure 2.45

Data input hold time

33.3

SS input setup time

tLEAD

tSPcyc

SS input hold time

tLAG

tSPcyc

Data output delay

tOD

33.3

Data output hold time

tOH

–10

Data rise and fall time

tDr, tDf

16.6

SS input rise and fall time

tSSLr, tSSLf

16.6

Slave access time

tSA

4 (PCLKA ≤ 60 MHz)

8 (PCLKA > 60 MHz)

tPcyc

Figure 2.45

Slave output release time

tREL

5 (PCLKA ≤ 60 MHz)

10 (PCLKA > 60 MHz)

tPcyc

tTXD

tRXS tRXH

TxDn

RxDn

SCKn

n = 0 to 9

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