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HT56R23 Datasheet(PDF) 49 Page - Holtek Semiconductor Inc |
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HT56R23 Datasheet(HTML) 49 Page - Holtek Semiconductor Inc |
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49 / 127 page ![]() HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Rev. 1.30 49 December 26, 2014 b 7 T n E T n O N T n M 0 T n M 1 b 0 T M R n C R e g i s t e r ( n = 1 ) N o t i m p l e m e n t e d , r e a d a s " 0 " E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e T n M 1 0 0 1 1 T n M 0 0 1 0 1 n o m o d e a v a i l a b l e e v e n t c o u n t e r m o d e t i m e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e O p e r a t i n g m o d e s e l e c t T i m e r c l o c k s o u r c e 1 : f S U B ( 3 2 7 6 8 H z o r 3 2 K R C ) 0 : f S Y S / 4 T n S Timer/Event Counter Control Register - TMRnC Timer Control Registers - TMR0C, TMR1C, TMR2C, TMR3C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. It is the Timer Control Register together with its corre- sponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate Timer Control Register is fully programmed with the right data to en- sure its correct operation, a process that is normally car- ried out during program initialisation. To choose which of the three modes the timer is to oper- ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer Control Register, which are known as the bit pair TnM1/TnM0, must be set to the re- quired logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, depending upon which timer is used, provides the basic on/off con- trol of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer Con- trol Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode, the ac- tive transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as TnE. An additional T1S bit in the 16-bit Timer/Event Counter control register is used to deter- mine the clock source for the Timer/Event Counter. |
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