W78E858

Publication Release Date: April 22, 2008

- 7 -

Revision A8

5.2.3

Software Protected Data Write

The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme

is enabled, any write operation requires a series of three-byte program commands (with specific data

to a specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not activated. This write

scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise

during system power-up or power-down. Once enabled, the software data protection will remain

enabled unless the disable commands are issued. To reset the device to unprotected mode, a six-byte

command sequence is required.

The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM

flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The

data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.

5.2.4

Command Codes for Software Data Protection Enable/Disable and Software Erase

BYTE

ENABLE WRITE PROTECT

DISABLE WRITE PROTECT

SOFTWARE ERASE

SEQUENCE

ADDRESS

DATA

ADDRESS

DATA

ADDRESS

DATA

0 Write

FFD5H

AAH

FFD5H

AAH

FFD5H

AAH

1 Write

FFAAH

55H

FFAAH

55H

FFAAH

55H

2 Write

FFD5H

A0H

FFD5H

80H

FFD5H

80H

3 Write

-

-

FFD5H

AAH

FFD5H

AAH

4 Write

-

-

FFAAH

55H

FFAAH

55H

5 Write

-

-

FFD5H

20H

FFD5H

10H

Auiliary RAM 512 Bytes

0000H

01FFH

0200H

EEPROM 128 Bytes

FF80H

FFFFH

External M em ory

Fig. On-Chip External Mem ory Addressed Mapping

(a) Standard 51 Series

5.3 Demo Code:

EEPROM_BASE EQU

FF80H