WM8761 datasheet(8/23 Pages) CIRRUS

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WM8761

Production Data

PD, Rev 4.6, October 2011

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

VDD = 5V, GND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK Master clock pulse width high

tMCLKH

MCLK Master clock pulse width low

tMCLKL

MCLK Master clock cycle time

tMCLKY

MCLK Duty cycle

40:60

60:40

Time from MCLK stopping to power

down.

1.5

s

DIGITAL AUDIO INTERFACE

BCKIN

LRCIN

BCH

BCL

BCY

DIN

LRSU

LRH

Figure 2 Digital Audio Data Timing

Test Conditions

VDD = 5V, GND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCKIN cycle time

tBCY

BCKIN pulse width high

tBCH

BCKIN pulse width low

tBCL

LRCIN set-up time to BCKIN

rising edge

tLRSU

LRCIN hold time from

BCKIN rising edge

tLRH

DIN set-up time to BCKIN

rising edge

tDS

DIN hold time from BCKIN

rising edge

tDH

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