HT49C30L datasheet(13/43 Pages) HOLTEK

13 / 43 page

HT49R30A-1/HT49C30-1/HT49C30L

Rev. 1.10

September 25, 2002

It is recommended that a program not use the

²CALL

subroutine

² within the interrupt subroutine. It¢s because

interrupts often occur in an unpredictable manner or re-

quire to be serviced immediately in some applications.

At this time, if only one stack is left, and enabling the in-

terrupt is not well controlled, operation of the

²call² in the

interrupt subroutine may damage the original control se-

quence.

Oscillator configuration

The device provides three oscillator circuits for system

clocks, i.e., RC oscillator, crystal oscillator and 32768Hz

crystal oscillator, determined by options. No matter what

type of oscillator is selected, the signal is used for the

system clock. The HALT mode stops the system oscilla-

tor (RC and crystal oscillator only) and ignores external

signal to conserve power. The 32768Hz crystal oscilla-

tor (system oscillator) still runs at HALT mode. If the

32768Hz crystal oscillator is selected as the system os-

cillator, the system oscillator is not stopped; but the in-

struction execution is stopped. Since the

(used as

system oscillator or oscillator) is also designed for tim-

ing purposes, the internal timing (RTC, time base, WDT)

operation still runs even if the system enters the HALT

mode.

Of the three oscillators, if the RC oscillator is used, an

external resistor between OSC1 and VSS is required,

and the range of the resistance should be from 24k

W to

W for HT49R30A-1/HT49C30-1 and from 560kW to

W for HT49C30L. The system clock, divided by 4, is

available on OSC2 with pull-high resistor, which can be

used to synchronize external logic. The RC oscillator

provides the most cost effective solution. However, the

frequency of the oscillation may vary with VDD, temper-

ature, and the chip itself due to process variations. It is

therefore, not suitable for timing sensitive operations

where accurate oscillator frequency is desired.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real

time clock. In this case, only the 32.768kHz crystal oscil-

lator can be applied. The crystal should be connected

between OSC3 and OSC4.

The RTC oscillator circuit can be controlled to oscillate

quickly by setting the

²QOSC² bit (bit 4 of RTCC). It is

recommended to turn on the quick oscillating function

upon power on, and then turn it off after 2 seconds.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Although

the system enters the power down mode, the system

clock stops, and the WDT oscillator still works with a pe-

riod of approximately 78

ms. The WDT oscillator can be

disabled by options to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by options. But if the WDT is disabled, all exe-

cutions related to the WDT lead to no operation.

The WDT time-out period is fS/2

15 ~f

S/2

16.

If the WDT clock source chooses the internal WDT oscil-

lator, the time-out period may vary with temperature,

VDD, and process variations. On the other hand, if the

clock source selects the instruction clock and the

²HALT² instruction is executed, WDT may stop counting

and lose its protecting purpose, and the logic can only

be restarted by an external logic.

When the device operates in a noisy environment, using

the on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT can stop the system clock.

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a

²warm reset², and only

the PC and SP are reset to zero. To clear the contents of

the WDT, there are three methods to be adopted, i.e.,

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 4

O S C 2

V D D

3 2 7 6 8 H z C r y s t a l /

R T C O s c i l l a t o r

V D D

4 7 0 p .

O S C 3

O S C 4

System oscillator

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