ICS93V850 datasheet(7/8 Pages) ICST

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ICS93V850

Preliminary Product Preview

0423H—07/03/03

Recommended Layout for the ICS93V850

General Layout Precautions:

Use copper flooded ground on the top signal layer under the

clock buffer

The area under U1 on the right is an example.

Flood over the ground vias.

Use power vias for power and ground. Vias 20 mil or

larger in diameter have lower high frequency impedance.

Vias for signals may be minimum drill size.

Make all power and ground traces are as wide as the via

pad for lower inductance.

VAA for pin 16 has a low pass RC filter to decouple the

digital and analog supplies. The 4.7uF capacitors may be

replaced with a single low ESR device with the same

total capacitance. VAA is routed on a outside signal

layer. Do not cut a power or ground plane and route in it.

Notice that ground vias are never shared.

When ever possible,

VCC (net V2P5 in the schematic)

pins have a decoupling capacitor. Power is always routed

from the plane connection via to the capacitor pad to the

VCC pin on the clock buffer. Moats or plane cuts are not

used to isolate power.

Differential mode clock output traces are routed:

With a ground trace between the pairs. Trace is

grounded on both ends.

Without a ground trace, clock pairs are routed with a

separation of at least 5 times the thickness of the

dielectric. If the dielectric thickness is 4.5 mil, the

trace separation is at least 18 mils.

Terminate differential CLK_IN and FB_IN traces after

routing to buffer pads.

Component Values:

Ref Desg.

Value

Description

Package

C1,C4,C5,

C7,C11,C12

.01uF

CERAMIC MLC

0603

C2,C3,C8,

4.7uF

CERAMIC MLC

1206

C10

.22uF

CERAMIC MLC

0603

2200pF

CERAMIC MLC

0603

R9,R12

120

Ω

0603

4.7

Ω

0603

ICS93701AG

TSSOP48

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