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TDA2EX Datasheet(PDF) 71 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 391 page  71 TDA2EG-17 www.ti.com SPRS969B – AUGUST 2016 – REVISED JUNE 2017 Submit Documentation Feedback Product Folder Links: TDA2EG-17 Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated Table 4-13. McASP Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL Multichannel Audio Serial Port 6 mcasp6_axr0 McASP6 Transmit/Receive Data IO A18 mcasp6_axr1 McASP6 Transmit/Receive Data IO B17 mcasp6_axr2 McASP6 Transmit/Receive Data IO C14 mcasp6_axr3 McASP6 Transmit/Receive Data IO B15 mcasp6_ahclkx McASP6 Transmit High-Frequency Master Clock O J24 mcasp6_aclkx(1) McASP6 Transmit Bit Clock IO B16 mcasp6_fsx McASP6 Transmit Frame Sync IO B18 mcasp6_aclkr(1) McASP6 Receive Bit Clock IO B16 mcasp6_fsr McASP6 Receive Frame Sync IO B18 Multichannel Audio Serial Port 7 mcasp7_aclkr(1) McASP7 Receive Bit Clock I/O IO E16 mcasp7_aclkx(1) McASP7 Transmit Bit Clock I/O IO E16 mcasp7_ahclkx McASP7 Transmit High-Frequency Master Clock O H24 mcasp7_axr0 McASP7 Transmit/Receive Data I/O IO A19 mcasp7_axr1 McASP7 Transmit/Receive Data I/O IO E17 mcasp7_axr2 McASP7 Transmit/Receive Data I/O IO D16 mcasp7_axr3 McASP7 Transmit/Receive Data I/O IO D17 mcasp7_fsr McASP7 Receive Frame Sync I/O IO F16 mcasp7_fsx McASP7 Transmit Frame Sync I/O IO F16 Multichannel Audio Serial Port 8 mcasp8_aclkr(1) McASP8 Receive Bit Clock I/O IO D20 mcasp8_aclkx(1) McASP8 Transmit Bit Clock I/O IO D20 mcasp8_ahclkx McASP8 Transmit High-Frequency Master Clock I/O O H25 mcasp8_axr0 McASP8 Transmit/Receive Data I/O IO B20 mcasp8_axr1 McASP8 Transmit/Receive Data I/O IO C19 mcasp8_fsr McASP8 Receive Frame Sync I/O IO C20 mcasp8_fsx McASP8 Transmit Frame Sync I/O IO C20 (1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any non monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS. 4.3.13 USB NOTE For more information, see: Serial Communication Interface / SuperSpeed USB DRD Subsystem section of the device TRM. Table 4-14. Universal Serial Bus Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL Universal Serial Bus 1 usb1_dm USB1 USB2.0 differential signal pair (negative) IODS AB7 usb1_dp USB1 USB2.0 differential signal pair (positive) IODS AC6 usb1_drvvbus USB1 Drive VBUS signal O AD3 usb_rxn0(1) USB1 USB3.0 receiver negative lane IDS AE5 usb_rxp0(1) USB1 USB3.0 receiver positive lane IDS AD6 usb_txn0(1) USB1 USB3.0 transmitter negative lane ODS AE3 usb_txp0(1) USB1 USB3.0 transmitter positive lane ODS AD4 |
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