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LP5569 Datasheet(PDF) 61 Page - Texas Instruments |
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LP5569 Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 86 page  61 LP5569 www.ti.com SNVSAP8 – JULY 2017 Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Figure 64. MASTER_FADER3 Register 7 6 5 4 3 2 1 0 master_fader3 R/W-0h Table 59. MASTER_FADER3 Register Field Descriptions Bit Field Type Reset Description 7–0 master_fader3 R/W 0h Master fader3 is controlled by engine 3. 8.6.1.46 MASTER_FADER_PWM Register (Address = 4Ah) [reset = 0h] MASTER_FADER_PWM is shown in Figure 65 and described in Table 60. Return to Summary Table. Figure 65. MASTER_FADER_PWM Register 7 6 5 4 3 2 1 0 master_fader_pwm R-0h Table 60. MASTER_FADER_PWM Register Field Descriptions Bit Field Type Reset Description 7–0 master_fader_pwm R 0h PWM input duty cycle. 8.6.1.47 ENGINE1_PROG_START Register (Address = 4Bh) [reset = 0h] ENGINE1_PROG_START is shown in Figure 66 and described in Table 61. Return to Summary Table. Figure 66. ENGINE1_PROG_START Register 7 6 5 4 3 2 1 0 prog_start_addr1 R/W-0h Table 61. ENGINE1_PROG_START Register Field Descriptions Bit Field Type Reset Description 7–0 prog_start_addr1 R/W 0h Engine 1 program start address. 8.6.1.48 ENGINE2_PROG_START Register (Address = 4Ch) [reset = 0h] ENGINE2_PROG_START is shown in Figure 67 and described in Table 62. Return to Summary Table. Figure 67. ENGINE2_PROG_START Register 7 6 5 4 3 2 1 0 prog_start_addr2 R/W-0h Table 62. ENGINE2_PROG_START Register Field Descriptions Bit Field Type Reset Description 7–0 prog_start_addr2 R/W 0h Engine 2 program start address. |
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