AMD

2-354

PALCE29MA16H-25

Table 1a. PALCE29MA16 I/O Logic Macrocell Architecture Selections

Storage Element

1

Register

0

Latch

I/O Cell

1

Output Cell

0

Input Cell

Output Polarity

1

Active LOW

0

Active HIGH

Output Type

1

Combinatorial

0

Register/Latch

Feedback*

1

Register/Latch

0

I/O

*Applies to macrocells with single feedback only.

Table 1b. PALCE29MA16 I/O Logic Macrocell Clock Polarity and Output Enable Selections

Clock Edge/Latch Enable Level

1

1

CLK/

LE pin positive-going edge, active-LOW LE*

1

0

CLK/

LE pin negative-going edge, active-HIGH LE*

0

1

CLK/

LE PT positive-going edge, active-LOW LE*

0

0

CLK/

LE PT negative-going edge, active-HIGH LE*

Output Buffer Control

1

1

Pin-Controlled Three-State Enable

1

0

PT-Controlled Three-State Enable

0

1

Permanently Enabled (Output only)

0

0

Permanently Disabled (Input only)

Notes:

1 = Erased State (Charged or disconnected).

0 = Programmed State (Discharged or connected).

*Active-LOW LE means that data is stored when the

is transparent when the