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ACEX1 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # ACEX1
Description  Programmable Logic Device Family
PDF  86 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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ACEX1 Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
–
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2
for 5.0-V operation
–
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
–
Operate with a 2.5-V internal supply voltage
–
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
–
ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
–
Built-in, low-skew clock distribution trees
–
100% functional testing of all devices; test vectors or scan chains
are not required
–
Pull-up on I/O pins before and during configuration
s
Flexible interconnect
–
FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Tri-state emulation that implements internal tri-state buses
–
Up to six global clock signals and four global clear signals
s
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Open-drain option on each I/O pin
–
Programmable output slew-rate control to reduce switching
noise
–
Clamp to VCCIO user-selectable on a pin-by-pin basis
–
Supports hot-socketing



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