WM8978GEFLSLASHV datasheet(27/78 Pages) WOLFSON

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WM8978

PP Rev 1.7 January 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

ADCVOLL

[7:0]

11111111

( 0dB )

Left ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

R15

Left channel

ADC Digital

Volume

ADCVU

Not

latched

ADC left and ADC right volume do not

update until a 1 is written to ADCVU (in

reg 16 or 17)

7:0

ADCVOLR

[7:0]

11111111

( 0dB )

Right ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

R16

Right channel

ADC Digital

Volume

ADCVU

Not

latched

ADC left and ADC right volume do not

update until a 1 is written to ADCVU (in

reg 16 or 17)

Table 15 ADC Digital Volume Control

INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)

The WM8978 has an automatic PGA gain control circuit, which can function as an input peak limiter

or as an automatic level control (ALC).

In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal

goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too

large for the input range of the ADC. When the signal returns to a level below the threshold, the

PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain

above its static level.

Figure 10 Input Peak Limiter Operation

WM8978GEFL/V Datasheet(PDF) 27 Page - Wolfson Microelectronics plc

WM8978GEFL/V Datasheet(HTML) 27 Page - Wolfson Microelectronics plc

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