10

Integrated

Circuit

Systems, Inc.

ICS9DB104

0767C—07/19/04

Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output

to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There

SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.

SRC_STOP# - Assertion (transition from '1' to '0')

All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is

2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all

stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.

SRC_STOP# - De-assertion (transition from '0' to '1')

The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must

be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two

consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.

SRC_STOP#

PWRDWN#

SRC_Stop#

DIF (Free Running)

DIF# (Free Running)

DIF (Stoppable)

DIF# (Stoppable)

1mS

PWRDWN#

SRC_Stop#

DIF (Free Running)

DIF# (Free Running)

DIF (Stoppable)

DIF# (Stoppable)

1mS

SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)

SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)