Z53C80SCSI datasheet(16/40 Pages) ZILOG

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Z53C80 SCSI

PS97SCC0200

ZILOG

FUNCTIONAL DESCRIPTION (Continued)

A phase mismatch prevents the recognition of /REQ and

removes the chip from the bus during an Initiator send

operation (/DB7-/DB0 and /DBP will not be driven even

through the Assert Data Bus bit (Initiator Command Register,

bit 0). This may be disabled by resetting the DMA Mode bit

(Note: It is possible for this interrupt to occur when

connected as a Target if another device is driving the

phase lines to a different state).

The proper values for the Bus and Status Register and the

Current SCSI Bus Status Register are displayed in Figures

23 and 24, respectively.

Loss of BSY. If the Monitor Busy bit (bit 2) in the Mode

signal goes FALSE for at least a bus-settle delay. This

interrupt is disabled by resetting the Monitor Busy bit.

Figure 25. Bus and Status Register

Figure 26. Current SCSI Bus Status Register

Figure 23. Bus and Status Register

Figure 24. Current SCSI Bus Status Register

/DBP

/SEL

I//O

C//D

/MSQ

/REQ

/BSY

/RST

XX00

/ACK

/ATN

Busy Error

Phase Match

Interrupt Request Active

Parity Error

DMA Request

End of DMA

000100

/ACK

/ATN

Busy Error

Phase Match

Interrupt Request Active

Parity Error

DMA Request

End of DMA

1X10

/DBP

/SEL

I//O

C//D

/MSQ

/REQ

/BSY

/RST

1XXXX

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