High-Performance PWM Controller

EC3228

Page 11 of 16

3G15N-Rev.P002

Function Description(Cont.)

switching frequency.

During soft-start stage before the PGOOD pin is ready, the

under-voltage protection is prohibited. The over-voltage and

current-limit protection functions are enabled. If the output capacitor

has residue voltage before start-up, both low-side and high-side

MOSFETs are in off-state until the internal digital soft-start voltage

equals to the VFB voltage. This will ensure that the output voltage starts

from its existing voltage level. In the event of under-voltage,

over-temperature, or shutdown, the chip enables the soft-stop

function. The soft-stop function discharges the output voltage to the

GND. The duration of the discharge time is 8ms.

Power OK Indicator

The EC3228 features an open-drain POK pin to indicate output

regulation status. In normal operation, when the output voltage rises

90% of its target value, the POK goes high after 63us internal delay.

When the output voltage outruns 70% or 125% of the target voltage,

POK signal will be pulled low immediately.

Since the FB pin is used for both feedback and monitoring purposes, the

output voltage deviation can be coupled directly to the FB pin by the

capacitor in parallel with the voltage divider as shown in the typical

applications. In order to prevent false POK from dropping, capacitors

need to parallel at the output to confine the voltage deviation with

severe load step transient.

Under-Voltage Protection (UVP)

In the operational process, if a short-circuit occurs, the output voltage

will drop quickly. When load current is bigger than current-limit

threshold value, the output voltage will fall out of the required

regulation range. The under voltage protection circuit continually

monitors the FB voltage after soft-start is completed. If a load step is

strong enough to pull the output voltage lower than the under voltage

threshold, the under-voltage threshold is 70% of the nominal output

voltage, the internal UVP delay counter starts to count. After 16s

de-bounce time, the device turns off both high-side and low-side

MOSEFET with latched and starts a soft-stop process to shut down the

output gradually. Toggling enable pin to low or recycling VCC, will clear

the latch and bring the chip back to operation.

Over-Voltage Protection (OVP)

The over-voltage function monitors the output voltage by FB pin. When

the FB voltage increases over 125% of the reference voltage due to the

high-side MOSFET failure or for other reasons, the over-voltage

protection comparator designed with a 1.5s noise filter will force the

low side MOSFET gate driver fully turn on and latch high. This action

actively pulls down the output voltage. This OVP scheme only clamps

the voltage overshoot and does not invert the output voltage when

otherwise activated with a continuously high output from low-side

Over-Voltage Protection (OVP) (Cont.)

MOSFET driver. It’s a common problem for OVP schemes with a latch.

Once an over-voltage fault condition is set, it can only be reset by

toggling EN, VCC power-on-reset signal.

Current-Limit

The current-limit circuit employs a “valley” current-sensing algorithm

(See Figure 2). The EC3228 uses the low-side MOSFET’s RDS(ON) of the

synchronous rectifier as a current-sensing element. If the magnitude of

the current-sense signal at PHASE pin is above the current limit

threshold, the PWM is not allowed to initiate a new cycle. The actual

peak current is greater than the current limit threshold by an amount

equals to the inductor ripple current. Therefore, the exact current-limit

characteristic and maximum load capability are the functions of the

sense resistance, inductor value, and input voltage