LTC1850CFW datasheet(10/28 Pages) LINER

10 / 28 page

LTC1850/LTC1851

18501f

PI FU CTIO S

CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can

be used single ended relative to the analog input common

pin (COM) or differentially in pairs (CH0 and CH1, CH2 and

CH3, CH4 and CH5, CH6 and CH7).

COM (Pin 9): Analog Input Common Pin. For single-ended

operation (DIFF = 0), COM is the “–” analog input. COM is

disabled when DIFF is high.

REFOUT (Pin 10): Internal 2.5V Reference Output. Re-

quires bypass to analog ground plane with 1

µF.

REFIN (Pin 11): Reference Mode Select/Reference Buffer

Input. REFIN selects the Reference mode and acts as the

reference buffer Input. REFIN tied to ground will produce

2.048V on the REFCOMP pin. REFIN tied to the positive

supply disables the reference buffer to allow REFCOMP to

be driven externally. For voltages between 1V and 2.6V,

the reference buffer produces an output voltage on the

REFCOMP pin equal to 1.6384 times the voltage on REFIN

(4.096V on REFCOMP for a 2.5V input on REFIN).

REFCOMP (Pin 12): Reference Buffer Output. REFCOMP

sets the full-scale input span. The reference buffer pro-

duces an output voltage on the REFCOMP pin equal to

1.6384 times the voltage on the REFIN pin (4.096V on

REFCOMP for a 2.5V input on REFIN). REFIN tied to

ground will produce 2.048V on the REFCOMP pin.

REFCOMP can be driven externally if REFIN is tied to the

positive supply. Requires bypass to analog ground plane

with 10

µF tantalum in parallel with 0.1µF ceramic or 10µF

ceramic.

GND (Pin 13): Ground. Tie to analog ground plane.

VDD (Pin 14): 5V Supply. Short to Pin 15.

VDD (Pin 15): 5V Supply. Bypass to GND with 10µF

tantalum in parallel with 0.1

µF ceramic or 10µF ceramic.

GND (Pin 16): Ground for Internal Logic. Tie to analog

ground plane.

DIFFOUT/S6 (Pin 17): Three-State Digital Data Output.

Active when RD is low. Following a conversion, the single-

ended/differential bit of the present conversion is available

on this pin concurrent with the conversion result. In

Readback mode, the single-ended/differential bit of the

current sequencer location (S6) is available on this pin.

The output swings between OVDD and OGND.

A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): Three-

State Digital MUX Address Outputs. Active when RD is

low. Following a conversion, the MUX address of the

present conversion is available on these pins concurrent

with the conversion result. In Readback mode, the MUX

address of the current sequencer location (S5-S3) is

available on these pins. The outputs swing between OVDD

and OGND.

D9/S2 (Pin 21, LTC1850): Three-State Digital Data Out-

put. Active when RD is low. Following a conversion, bit 9