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LTC3832 Datasheet(PDF) 7 Page - Linear Technology

Part # LTC3832
Description  High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation
PDF  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3832 Datasheet(HTML) 7 Page - Linear Technology

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7
LTC3832/LTC3832-1
sn3832 3832fs
PI FU CTIO S
FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to VCC slows it down.
IMAX (Pin 12/NA): Current Limit Threshold Set. IMAX sets
the threshold for the internal current limit comparator. If
IFB drops below IMAX with G1 on, the LTC3832 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1
µF decoupling capacitor across this
resistor to filter switching noise.
IFB (Pin 13/NA): Current Limit Sense. Connect this pin to
the switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
VCC (Pin 14/Pin 7): Power Supply Input. All low power
internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
VIN supply at the drain of Q1. This pin requires a 4.7µF
bypass capacitor. The LTC3832-1has VCC and PVCC2 tied
together at Pin 7 and requires a 10
µF bypass capacitor to
GND.
PVCC2 (Pin 15/Pin 7): Power Supply Input for G2. Connect
this pin to the main high power supply.
G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PVCC2. It remains low
when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).
BLOCK DIAGRA
–
+
–
+
R
S
PVCC1
G1
PVCC2
G2
PGND
FB
SENSE+
VREF
VREF + 10%
18k
5.7k
SENSE–
3832 BD
BG
Q
Q
R
POR
S
FFBG
ENABLE
G2
Q
PWM
QSS
VREF
VREF + 10%
MAX
ERR
12
µA
INTERNAL
OSCILLATOR
100
µs DELAY
SHDN
FREQSET
COMP
SS
POWER DOWN
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
+
–
CC
2.2V
QC
1.2V
PVCC1
VCC + 2.5V
12
µA
DISABLE
ILIM
IMAX
IFB
VCC
GND
–
+
V
(LTC3832)



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