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Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 23 of 36

Figure 42 and Figure 43 show the AD4002/AD4006/AD4010

SNR and THD performance using the ADA4077-1 (supply

current per amplifier (ISY) = 400 µA), and ADA4610-1 (ISY =

1.50 mA) precision amplifiers when driving the AD4002/AD4006/

AD4010 at full throughput for high-Z mode both enabled and

disabled with various RC filter values. These amplifiers achieve

TBD dB to TBD dB typical SNR and close to TBD dB typical

TBD with high-Z enabled for a 2.27 MHz RC bandwidth. THD

is approximately TBD dB better with high-Z mode enabled,

even for large R values greater than 200 Ω. SNR maintains close

to TBD dB even with a very low RC filter cutoff.

When high-Z mode is enabled, the ADC consumes approximately

2 mW per MSPS extra power; however, this is still significantly

lower than using dedicated ADC drivers like the ADA4807-1.

For any system, the front end usually limits the overall ac/dc

performance of the signal chain. It is evident from the data

sheets of the selected precision amplifiers shown in Figure 42

and Figure 43 that their own noise and distortion performance

dominates the SNR and THD specification at a certain input

frequency.

TBD

Figure 42. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, VREF = 5 V, 25°C

TBD

Figure 43. THD vs. RC Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, VREF = 5 V, 25°C

Long Acquisition Phase

The AD4002/AD4006/AD4010 also feature a very fast

conversion time of 290 ns, which results in a long acquisition

phase. The acquisition is further extended by a key feature of

the AD4002/AD4006/AD4010: the ADC returns to the

acquisition phase typically 100 ns before the end of the conversion.

This feature provides an even longer time for the ADC to acquire

the new input voltage. A longer acquisition phase reduces the

settling requirement on the driving amplifier, and a lower power/

bandwidth amplifier can be chosen. The longer acquisition

phase means that a lower RC filter (represented by R and C in

Figure 33 and Figure 34) cutoff can be used, which means a

noisier amplifier can also be tolerated. A larger value of R can

be used in the RC filter with a corresponding smaller value of C,

reducing amplifier stability concerns without affecting distortion

performance significantly. A larger value of R also results in

reduced dynamic power dissipation in the amplifier.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such as

the ADR4550. Use a low power reference such as the ADR3450

at the expense of a slight decrease in the noise performance. It is

recommended to use a reference buffer such as the ADA4807-1

between the reference and the ADC reference input. It is important

to consider the optimum capacitance necessary to keep the

reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section (that is, a 10 µF

ceramic chip capacitor, CREF).

POWER SUPPLY

The AD4002/AD4006/AD4010 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and 5.5 V.

To reduce the number of supplies needed, VIO and VDD can be

tied together for 1.8 V operation. The ADP7118 low noise,

CMOS, low dropout (LDO) linear regulator is recommended to

power the VDD and VIO pins. The AD4002/AD4006/AD4010

are independent of power supply sequencing between VIO and

VDD. Additionally, the AD4002/AD4006/AD4010 are insensitive

to power supply variations over a wide frequency range, as

shown in Figure 44.

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