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MT9V403 Datasheet(PDF) 5 Page - Micron Technology

Part # MT9V403
Description  1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
PDF  33 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT9V403 Datasheet(HTML) 5 Page - Micron Technology

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1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
09005aef80c07280
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V403_DS.fm - Rev. B 1/04 EN
5
©2004 Micron Technology. Inc.
Figure 5: Master Mode Row Timing Diagram
NOTE:
Horizontal blanking is nominally 35 rows, and may be increased using register 5.
In master mode the frame rate is controlled by
inserting vertical and/or horizontal blanking periods
during readout, or by changing the input master clock
(SYSCLK) frequency (i.e., slowing the sensor down), or
by changing the number of rows being readout (i.e.,
window size). Table 2 shows some examples of how the
frame rate changes with window resolution and clock
speed.
Table 2:
Frame Rate vs. Resolution and Clock Speed
No blanking, exposure < readout
When
horizontal
blanking
is
utilized,
the
ROW_VALID stays LOW for an additional user-pro-
grammable number of clock cycles after each row
readout. As a result the row time becomes:
RT = (1 + 66 6+ 4 + HB) x (1/fsysclk)
where HB is the horizontal blanking in SYSCLK
cycles (255 clock maximum) specified in register 5.
When vertical blanking is utilized, the FRAME_
VALID signal stays LOW for an additional user pro-
grammable number of rows after the frame is readout
(if exposure time < readout time) or exposed (if expo-
sure time > readout time). Table 3 on page 6 shows the
various scenarios for calculating the frame time, where
VB is the vertical blanking in rows (255 rows maxi-
mum) specified in register 6. The default vertical
blanking is one SYSCLK cycle, so the true vertical
blanking time is the number of blanking rows pro-
grammed plus one clock cycle.
Horizontal Blanking
SYSCLK
(input)
ROW _VALID
(output)
DATA [9:0]
(output)
1
XXX
XXX
12
653
671
671
+
169
1
12
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
9
10
648
649
910
(
)
(
)
652
RESOLUTION (# ROWS)
CLOCK SPEED (SYSCLK)
FRAME RATE (FRAMES/SECOND)
502 (full resolution)
66 MHz
196
251
66 MHz
392
125
66 MHz
784
63
66 MHz
1568
502 (full resolution)
24 MHz
70
251
24MHz
140
125
24 MHz
280
63
24 MHz
560
502 (full resolution)
10 MHz
30



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