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AD7902 Datasheet(PDF) 20 Page - Analog Devices

Part # AD7902
Description  Dual Pseudo Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7902 Datasheet(HTML) 20 Page - Analog Devices

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Data Sheet
AD7902
Rev. B | Page 19 of 28
CS Mode, 3-Wire Interface with Busy Indicator
CS mode, using a 3-wire interface with a busy indicator, is usually
used when a single AD7902 is connected to an SPI-compatible
digital host having an interrupt input.
The connection diagram is shown in Figure 40, and the
corresponding timing is shown in Figure 41.
With SDIx tied to VIOx, a rising edge on CNVx initiates
a conversion, selects CS mode, and forces SDOx to high
impedance. SDOx is maintained in high impedance until the
completion of the conversion, regardless of the state of CNVx.
Prior to the minimum conversion time, CNVx can be used to
select other SPI devices, such as analog multiplexers, but CNVx
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDOx goes from high
impedance to low impedance. With a pull-up on the SDOx line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7902 then
enters the acquisition phase and powers down. The data bits are
then clocked out, MSB first, by subsequent SCKx falling edges.
The data is valid on both SCKx edges. Although the rising edge
can be used to capture the data, a digital host using the SCKx
falling edge allows a faster reading rate, provided that it has an
acceptable hold time. After the optional 17th SCKx falling edge
or when CNVx goes high (whichever occurs first), SDOx
returns to high impedance.
If multiple ADCs are selected at the same time, the SDOx output
pin handles this contention without damage or induced latch-up.
Meanwhile, it is recommended that this contention be kept as
short as possible to limit extra power dissipation.
Figure 40. CS Mode, 3-Wire Interface with a Busy Indicator Connection Diagram (SDIx High)
Figure 41. CS Mode, 3-Wire Interface with a Busy Indicator Serial Interface Timing (SDIx High)
AD7902
SDIx
SDOx
CNVx
SCKx
CONVERT
DATA IN
CLK
DIGITAL HOST
VIOx
IRQ
VIOx
47kΩ
tCONV
tCNVH
tCYC
ACQUISITION
ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCKx
CNVx
SDIx = 1
SDOx
D15
D14
D1
D0
tHSDO
1
2
3
15
16
17
tDSDO
tDIS



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