PIC12CE673 datasheet(54/116 Pages) MICROCHIP

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PIC12CE67X

DS40181B-page 54

Preliminary

9.5

Interrupts

There are four sources of interrupt:

The interrupt control register (INTCON) records individ-

ual interrupt requests in ﬂag bits. It also has individual

and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s ﬂag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous

registers.

Individual

interrupt

bits

are

set

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

Interrupt Sources

TMR0 overﬂow interrupt

External interrupt GP2/INT pin

GPIO Port change interrupts (pins GP0, GP1, GP3)

A/D Interrupt

Note:

Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

The GP2/INT, GPIO port change interrupt and the

TMR0 overﬂow interrupt ﬂags are contained in the

INTCON register.

The peripheral interrupt ﬂag ADIF, is contained in the

special function register PIR1. The corresponding

interrupt enable bit is contained in special function reg-

ister PIE1, and the peripheral interrupt enable bit is

contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as GPIO change

interrupt, the interrupt latency will be three or four

instruction cycles. The exact latency depends when the

interrupt event occurs (Figure 8-15). The latency is the

same for one or two cycle instructions. Individual inter-

rupt ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 9-14: INTERRUPT LOGIC

GPIF

GPIE

T0IF

T0IE

GIE

Wakeup

(If in SLEEP mode)

Interrupt to CPU

PEIE

ADIF

ADIE

INTF

INTE

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