PIC12CE673-04ESLASHP datasheet(92/116 Pages) MICROCHIP

92 / 116 page

PIC12CE67X

DS40181B-page 92

Preliminary

FIGURE 12-3: CLKOUT AND I/O TIMING

TABLE 12-4:

CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Units Conditions

10*

TosH2ckL

OSC1

↑ to CLKOUT↓

—

Note 1

11*

TosH2ckH

OSC1

↑ to CLKOUT↑

—

Note 1

12*

TckR

CLKOUT rise time

—

Note 1

13*

TckF

CLKOUT fall time

—

Note 1

14*

TckL2ioV

CLKOUT

↓ to Port out valid

—

0.5TCY + 20

Note 1

15*

TioV2ckH

Port in valid before CLKOUT

↑

0.25TCY + 25

—

Note 1

16*

TckH2ioI

Port in hold after CLKOUT

↑

—

Note 1

17*

TosH2ioV

OSC1

↑ (Q1 cycle) to

Port out valid

—

80 - 100

18*

TosH2ioI

OSC1

↑ (Q2 cycle) to

Port input invalid (I/O in hold time)

TBD

—

19*

TioV2osH

Port input valid to OSC1

↑ (I/O in setup time)

TBD

—

20*

TioR

Port output rise time

PIC12CE67X

—

21*

TioF

Port output fall time

PIC12CE67X

—

22††*

Tinp

INT pin high or low time

—

23††*

Trbp

GPIO change INT high or low time

—

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1:

Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.

Note: Refer to Figure 12-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

20, 21

old value

new value

PIC12CE673-04E/P Datasheet(PDF) 92 Page - Microchip Technology

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