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VSC7146RH Datasheet(PDF) 14 Page - Vitesse Semiconductor Corporation |
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VSC7146RH Datasheet(HTML) 14 Page - Vitesse Semiconductor Corporation |
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14 / 19 page ![]() VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 2.5Gb/s, 20-Bit Transceiver Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 8/28/00 G52162-0 Rev. 2.7 Table 6: Pin Identifications Pin # Name Description 2, 4, 6, 9, 11, 14, 16, 18, 20, 23, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24 T[0:19] INPUTS - TTL: Transmit Data Bus, Bit 0 through Bit 19. 20-bit Transmit Character. Parallel data on this bus is clocked in on the rising edge of TBC. The data bit corresponding to T0 is transmitted first. 26 REF INPUT - TTL: Reference Clock. REF goes to the PLL/CMU circuitry and is multiplied 20 times 28 TBC INPUT - TTL: Transmit Byte Clock. This rising edge of this clock latches T[0:19] into the input register and provides the reference clock at 1/20th of the baud rate to the PLL. 74,75 TX+, TX- OUTPUTS - Differential (AC-coupling recommended): Transmitter Serial Outputs. These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. 65, 63, 59, 57, 55, 52, 50, 48, 45, 43, 64, 62, 58, 56, 54, 51, 49, 47, 44, 42 R[0:19] OUTPUTS - TTL: Receive Data Bus, Bits 0 thru 19. 20-bit received character. Parallel data on this bus can be sampled on the rising edge of RBC. R0 is the first bit received on RX+/RX-. 35 TXRATE INPUT - TTL: Transmitter Dual Rate Selector. LOW for half-speed operation (1.25Gb/s). HIGH for full-speed operation (2.5 Gbps). 79 RXRATE INPUT - TTL: Receiver Dual Rate Selector. LOW for half-speed operation (1.25Gb/s). HIGH for full-speed operation (2.5Gb/s). 29 BCMN INPUT - TTL: Backwards Compatibility Mode Selector. LOW to allow operation in previous ver- sion compatibility (no separate rate controls for transmitter and receiver). HIGH to allow operation with separate rate controls for transmitter and receiver. 36 EWRAP INPUT - TTL: Enable Internal WRAP Mode. LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled, TX+ = HIGH and TX- is LOW. 68, 67 RX+, RX- INPUTS - Differential (AC-coupling recommended): Receive Serial Inputs. The receiver inputs when EWRAP is LOW. 38, 39 RBC, RBCN OUTPUT - TTL: Recovered Byte Clock. Recovered clock and complement derived from 1/20th of the RX+/- data rate. The rising edge of RBC corresponds to a new word on R[0:19]. 34 EN_CDET INPUT - TTL: ENable Comma DETect. Enables COM_DET and word resynchroni- zation when HIGH. When LOW, keeps current word alignment and disables COM_DET. 37 COM_DET OUTPUT - TTL: COMma DETect. This output goes HIGH to indicate that R[0:6] contains a “comma” character (‘0011111’). COM_DET can be sampled on the rising edge of RBC. |
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