AD9683-170EBZ datasheet(3/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 2 of 44

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

ADC DC Specifications............................................................... 4

ADC AC Specifications ............................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 13

Equivalent Circuits......................................................................... 18

Theory of Operation ...................................................................... 19

ADC Architecture ...................................................................... 19

Analog Input Considerations.................................................... 19

Voltage Reference ....................................................................... 20

Clock Input Considerations...................................................... 21

Power Dissipation and Standby Mode .................................... 23

Digital Outputs ............................................................................... 24

JESD204B Transmit Top Level Description............................ 24

ADC Overrange and Gain Control.......................................... 29

DC Correction (DCC)................................................................... 31

DC Correction Bandwidth........................................................ 31

DC Correction Readback.......................................................... 31

DC Correction Freeze................................................................ 31

DC Correction Enable Bits ....................................................... 31

Serial Port Interface (SPI).............................................................. 32

Configuration Using the SPI..................................................... 32

Hardware Interface..................................................................... 32

SPI Accessible Features.............................................................. 33

Memory Map .................................................................................. 34

Reading the Memory Map Register Table............................... 34

Memory Map Register Table..................................................... 35

Memory Map Register Descriptions........................................ 39

Applications Information .............................................................. 43

Design Guidelines ...................................................................... 43

Outline Dimensions....................................................................... 44

Ordering Guide .......................................................................... 44

REVISION HISTORY

6/2016—Rev. C to Rev.D

Changes to Table 17........................................................................ 37

Change to JESD204B Link Control 1 (Address 0x5F) Section.......40

9/2015—Rev. B to Rev. C

Changes to General Description Section ...................................... 3

Changes to Nyquist Clock Input Options Section ..................... 21

Changes to JESD204B Overview Section.................................... 24

Changes to Figure 60...................................................................... 27

Change to Table 17 ......................................................................... 37

5/2014—Rev. A to Rev. B

Changed Minimum RF Clock Rate from 625 MHz to 500 MHz

(Throughout) .................................................................................... 6

Changes to SYNCINB+ Pin Description .................................... 11

Changes to Transfer Register Map Section ................................. 34

Changes to Register 0x3A ............................................................. 36

Changes to Register 0x6F, Register 0x70, Register 0x72,

Changes to JESD204B Link Control 2 (Address 0x60) Section.....40

2/2014—Rev. 0 to Rev. A

Changes to Data Output Parameters, Table 4................................8

Changes to Figure 3...........................................................................9

4/2013—Revision 0: Initial Version

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