74HC4024DB datasheet(2/18 Pages) PHILIPS

2 / 18 page

9397 750 13813

Product data sheet

Rev. 03 — 12 November 2004

2 of 18

Philips Semiconductors

74HC4024

7-stage binary ripple counter

Quick reference data

[1]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(C

L × VCC

× f

o) = sum of outputs.

Ordering information

Table 1:

Quick reference data

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tPHL, tPLH

propagation delay CP to

CL =15pF;

VCC =5V

-14

fmax

maximum clock frequency CL =15pF;

VCC =5V

MHz

input capacitance

3.5

CPD

power dissipation

capacitance

VI = GND to VCC [1] -25

Table 2:

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74HC4024N

−40 °C to +125 °C

DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

74HC4024D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HC4024DB

−40 °C to +125 °C

SSOP14

plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74HC4024PW

−40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package;

14 leads; body width 4.4 mm

SOT402-1

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