AD9216-80PCB datasheet(7/41 Pages) AD

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AD9216

Rev. A | Page 6 of 40

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

TMIN to TMAX, DCS enabled, unless otherwise noted.

Table 4.

AD9216BCPZ-65

AD9216BCPZ-80

AD9216BCPZ-105

Parameter

Temp

Test Level

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

105

MSPS

Minimum Conversion Rate

Full

MSPS

CLK Period

Full

15.4

12.5

9.5

CLK Pulse Width High

Full

4.6

4.4

3.8

CLK Pulse Width Low

Full

4.6

4.4

3.8

OUTPUT PARAMETERS1

Output Propagation Delay2 (tPD)

25°C

4.5

6.4

4.5

6.4

4.5

6.4

Valid Time3 (tV)

25°C

2.0

Output Rise Time (10% to 90%)

25°C

1.0

Output Fall Time (10% to 90%)

25°C

1.0

Output Enable Time4

Full

Cycle

Output Disable Time4

Full

Cycle

Pipeline Delay (Latency)

Full

Cycle

APERTURE

Aperture Delay (tA)

25°C

1.5

Aperture Uncertainty (tJ)

25°C

0.5

pS rms

Wake-Up Time5

25°C

OUT-OF-RANGE RECOVERY TIME

25°C

Cycle

1 CLOAD equals 5 pF maximum for all output switching parameters.

2 Output delay is measured from clock 50% transition to data 50% transition.

3 Valid time is approximately equal to the minimum output propagation delay.

4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective

channel outputs going into high impedance.

5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.

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