IRU3046 datasheet(12/20 Pages) IRF

12 / 20 page

Rev. 1.9

09/27/02

IRU3046

www.irf.com

From (18), R2 can be express as:

Set the zero of compensator to be half of FLC(SLAVE), the

compensator capacitor, C2, can be calculated as:

Using equations (20) and (21) we get the following val-

ues for R2 and C2.

LDO Section

Output Voltage Programming

Output voltage for LDO is programmed by reference volt-

age and external voltage divider. The Fb3 pin is the in-

verting input of the error amplifier, which is internally ref-

erenced to 1.25V. The divider is ratioed to provide 1.25V

at the Fb3 pin when the output is at its desired value.

The output voltage is defined by using the following equa-

tion:

Results to R7=1K

C2=6606pF; Choose: C2=6800pF

R2=16.45K;

Choose: R2=16.5K

LDO Power MOSFET Selection

The first step in selecting the power MOSFET for the

linear regulator is to select the maximum RDS(ON) based

on the input to the dropout voltage and the maximum

load current.

Results to: RDS(ON)(MAX) = 0.4

Note that since the MOSFET RDS(ON) increases with tem-

perature, this number must be divided by ~1.5 in order

to find the RDS(ON)(MAX) at room temperature. The IRLR2703

has a maximum of 0.065

V RDS(ON) at room temperature,

which meets our requirements.

Layout Consideration

The layout is very important when designing high fre-

quency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

Start to place the power components, make all the con-

nection in the top layer with wide, copper filled areas.

The inductor, output capacitor and the MOSFET should

be close to each other as possible. This helps to reduce

the EMI radiated by the power traces due to the high

switching currents through them. Place input capacitor

directly to the drain of the high-side MOSFET, to reduce

the ESR replace the single input capacitor with two par-

allel units. The feedback part of the system should be

kept away from the inductor and other noise sources,

and be placed close to the IC. In multilayer PCB use

one layer as power ground plane and have a control cir-

cuit ground (analog ground), to which all signals are ref-

erenced. The goal is to localize the high current path to

a separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout at a

single point.

R2 =

gm 3 RS1

p 3 FO2 3 L2 3 VOSC

VIN(SLAVE) - VOUT

---(20)

R10

VOUT2 = VREF

3 1+

(

)

For:

VOUT2 = 2.5V

VREF = 1.25V

R10 = 1K

RDS(ON) =

VIN3 - VOUT2

IOUT2

For:

VIN3 = 3.3V

VOUT2 = 2.5V

IOUT2 = 2A

H(Fo) =

gm3RS13R23

---(19)

VIN - VOUT

p3Fo3L23VOSC

FLC(SLAVE) =

3COUT

Fz =

FLC(SLAVE)

C2 =

---(21)

p 3 R2 3 Fz

Fb3

IRU3046

VOUT3

R10

Figure 9 - Programming the output voltage for LDO.

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