ADC12DL040 datasheet(7/26 Pages) NSC

7 / 26 page

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V

A =VD = +3.0V, VDR =

+2.5V, PD = 0V, V

REF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr =tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel

output mode. Boldface limits apply for T

J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 10)

Units

(Limits)

CLK, PD, OEA, OEB DIGITAL INPUT CHARACTERISTICS

IN(1)

Logical “1” Input Voltage

D = 3.6V

2.0

V (min)

IN(0)

Logical “0” Input Voltage

D = 3.0V

1.0

V (max)

IN(1)

Logical “1” Input Current

IN = 3.3V

µA

IN(0)

Logical “0” Input Current

IN = 0V

−10

µA

Digital Input Capacitance

DA0–DA11, DB0-DB11 DIGITAL OUTPUT CHARACTERISTICS

OUT(1)

Logical “1” Output Voltage

OUT = −0.5 mA

DR = 2.5V

2.3

V (min)

DR =3V

2.7

V (min)

OUT(0)

Logical “0” Output Voltage

OUT = 1.6 mA, VDR =3V

0.4

V (max)

TRI-STATE® Output Current

OUT = 2.5V or 3.3V

100

OUT = 0V

−100

Output Short Circuit Source

Current

OUT = 0V

−20

−I

Output Short Circuit Sink Current

OUT =VDR

OUT

Digital Output Capacitance

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

PD Pin = DGND, V

REF =VA

PD Pin = V

mA (max)

Digital Supply Current

PD Pin = DGND

PD Pin = V

D ,fCLK =0

mA (max)

Digital Output Supply Current

PD Pin = DGND, C

L = 5 pF (Note 14)

PD Pin = V

D,fCLK =0

Total Power Consumption

PD Pin = DGND, C

L = 5 pF (Note 15)

PD Pin = V

210

258

mW (max)

PSRR1

Power Supply Rejection Ratio

Rejection of Full-Scale Error with

A = 2.7V vs. 3.6V

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V

A =VD = +3.0V, VDR =

+2.5V, PD = 0V, External V

REF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr =tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,

parallel output mode. Boldface limits apply for T

J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 10)

Units

(Limits)

CLK1

Maximum Clock Frequency

MHz (min)

CLK2

Minimum Clock Frequency

MHz

Clock High Time

Duty Cycle Stabilizer On

12.5

ns (min)

Clock Low Time

Duty Cycle Stabilizer On

12.5

ns (min)

r,tf

Clock Rise and Fall Times

Duty Cycle Stabilizer On

ns (max)

Clock High Time

Duty Cycle Stabilizer Off

12.5

ns (min)

Clock Low Time

Duty Cycle Stabilizer Off

12.5

ns (min)

r,tf

Clock Rise and Fall Times

Duty Cycle Stabilizer Off

ns (max)

CONV

Conversion Latency

Parallel mode

Clock

Cycles

Data Output Delay after Rising

Clock Edge

Parallel mode

6.0

3.5

ns (min)

9.6

ns (max)

ADC12DL040 Datasheet(PDF) 7 Page - National Semiconductor (TI)

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