Z8L18006FSC datasheet(39/70 Pages) ZILOG

39 / 70 page

Z80180/Z8S180/Z8L180

Zilog

Enhanced Z180 Microprocessor

DS971800401

P R E L I M I N A R Y

1-39

ASCI CHANNEL CONTROL REGISTER A

MPE: Multi-Processor Mode Enable (bit 7). The ASCI

has a multiprocessor communication mode that utilizes an

extra data bit for selective communication when a number

of processors share a common serial bus. Multiprocessor

data format is selected when the MP bit in CNTLB is set to

1. If multiprocessor mode is not selected (MP bit in CNTLB

= 0), MPE has no effect. If multiprocessor mode is select-

ed, MPE enables or disables the “wake-up” feature as fol-

lows. If MBE is set to 1, only received bytes in which the

MPB (multiprocessor bit) = 1 can affect the RDRF and er-

ror flags. Effectively, other bytes (with MPB = 0) are “ig-

nored” by the ASCI. If MPE is reset to 0, all bytes, regard-

less of the state of the MPB data bit, affect the REDR and

error flags. MPE is cleared to 0 during RESET.

RE: Receiver Enable (bit 6). When RE is set to 1, the

ASCI transmitter is enabled. When TE is reset to 0, the

transmitter is disables and any transmit operation in

progress is interrupted. However, the TDRE flag is not re-

set and the previous contents of TDRE are held. TE is

cleared to 0 in IOSTOP mode during RESET.

TE: Transmitter Enable (bit 5). When TE is set to 1, the

ASCI receiver is enabled. When TE is reset to 0, the trans-

mitter is disabled and any transmit operation in progress is

interrupted. However, the TDRE flag is not reset and the

previous contents of TDRE are held. TE is cleared to 0 in

IOSTOP mode during RESET.

RTS0: Request to Send Channel 0 (bit 4 in CNTLA0

only). If bit 4 of the System Configuration Register is 0, the

RTS0/TxS pin has the RTS0 function. RTS0 allows the

ASCI to control (start/stop) another communication devic-

es transmission (for example, by connecting to that de-

vice’s CTS input). RTS0 is essentially a 1 bit output port,

having no side effects on other ASCI registers or flags.

Bit 4 in CNTLA1 is used.

CKA1D = 1, CKA1/TEND0 pin = TEND0

CKA1D = 0, CKA1/TEND0 pin = CKA1

Cleared to 0 on reset.

MPBR/EFR: Multiprocessor Bit Receive/Error Flag Re-

set (bit 3). When multiprocessor mode is enabled (MP in

CNTLB = 1), MPBR, when read, contains the value of the

MPB bit for the last receive operation. When written to 0,

the EFR function is selected to reset all error flags (OVRN,

FE, PE and BRK in the ASEXT Register) to 0. MPBR/EFR

is undefined during RESET.

Figure 33. ASCI Channel Control Register A

Bit

MPE

R/W

RTS0

MPBR/

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 0 (CNTLA0: I/O Address = 00H)

R/W

EFR

Bit

MPE

R/W

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 1 (CNTLA1: I/O Address = 01H)

R/W

MPBR/

EFR

CKA1D

Z8L18006FSC Datasheet(PDF) 39 Page - Zilog, Inc.

Z8L18006FSC Datasheet(HTML) 39 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL