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COPCJ820 Datasheet(PDF) 21 Page - National Semiconductor (TI) |
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COPCJ820 Datasheet(HTML) 21 Page - National Semiconductor (TI) |
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21 / 32 page  Instruction Set REGISTER AND SYMBOL DEFINITIONS Registers A 8-bit Accumulator register B 8-bit Address register X 8-bit Address register SP 8-bit Stack pointer register PC 15-bit Program counter register PU upper 7 bits of PC PL lower 8 bits of PC C 1-bit of PSW register for carry HC Half Carry GIE 1-bit of PSW register for global interrupt enable Symbols B Memory indirectly addressed by B register X Memory indirectly addressed by X register Mem Direct address memory or B MemI Direct address memory or B or Immediate data Imm 8-bit Immediate data Reg Register memory addresses F0 to FF (Includes B X and SP) Bit Bit number (0 to 7) w Loaded with Exchanged with Instruction Set ADD add A w A a MemI ADC add with carry A w A a MemI a C C w Carry HC w Half Carry SUBC subtract with carry A w A a MemI aC C w Carry HC w Half Carry AND Logical AND A w A and MemI OR Logical OR A w A or MemI XOR Logical Exclusive-OR A w A xor MemI IFEQ IF equal Compare A and MemI Do next if A e MemI IFGT IF greater than Compare A and MemI Do next if A l MemI IFBNE IF B not equal Do next if lower 4 bits of B i Imm DRSZ Decrement Reg skip if zero Reg w Reg b 1 skip if Reg goes to 0 SBIT Set bit 1 to bit Mem (bite 0 to 7 immediate) RBIT Reset bit 0 to bit Mem IFBIT If bit If bit Mem is true do next instr X Exchange A with memory A Mem LD A Load A with memory A w MemI LD mem Load Direct memory Immed Mem w Imm LD Reg Load Register memory Immed Reg w Imm X Exchange A with memory B A B (B w Bg1) X Exchange A with memory X A X (X w Xg1) LD A Load A with memory B A w B (B w Bg1) LD A Load A with memory X A w X (X w Xg1) LD M Load Memory Immediate B w Imm (B w Bg1) CLRA Clear A A w 0 INCA Increment A A w A a 1 DECA Decrement A A w A b 1 LAID Load A indirect from ROM A w ROM(PUA) DCORA DECIMAL CORRECT A A w BCD correction (follows ADC SUBC) RRCA ROTATE A RIGHT THRU C C x A7 x x A0 x C SWAPA Swap nibbles of A A7A4 A3A0 SC Set C C w 1 HC w 1 RC Reset C C w 0 HC w 0 IFC If C If C is true do next instruction IFNC If not C If C is not true do next instruction JMPL Jump absolute long PC w ii (ii e 15 bits 0 to 32k) JMP Jump absolute PC110 w i(i e 12 bits) JP Jump relative short PC w PC a r(ris b31 to a32 not 1) JSRL Jump subroutine long SP w PL SP-1 w PUSP-2PC w ii JSR Jump subroutine SP w PL SP-1 w PUSP-2PC11 0 w i JID Jump indirect PL w ROM(PUA) RET Return from subroutine SPa2PL w SP PU w SP-1 RETSK Return and Skip SPa2PL w SP PU w SP-1 Skip next instruction RETI Return from Interrupt SPa2PL w SP PU w SP-1 GIE w 1 INTR Generate an interrupt SP w PL SPb1 w PUSP-2PC w 0FF NOP No operation PC w PC a 1 http www nationalcom 21 |
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