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AD6655

Data Sheet

Rev. B | Page 38 of 84

NUMERICALLY CONTROLLED OSCILLATOR (NCO)

FREQUENCY TRANSLATION

This processing stage comprises a digital tuner consisting of

a 32-bit complex numerically controlled oscillator (NCO). The

two channels of the AD6655 share a single NCO. The NCO is

optional and can be bypassed by clearing Bit 0 of Register 0x11D.

This NCO block accepts a real input from the ADC stage and

outputs a frequency translated complex (I and Q) output.

The NCO frequency is programmed in Register 0x11E,

8-bit registers make up a 32-bit unsigned frequency programming

word. Frequencies between −CLK/2 and +CLK/2 are represented

using the following frequency words:



0x8000 0000 represents a frequency given by −CLK/2.



0x0000 0000 represents dc (frequency = 0 Hz).



0x7FFF FFFF represents CLK/2 − CLK/232.

Use the following equation to calculate the NCO frequency:

CLK

Mod

NCO_FREQ

)

(





where:

NCO_FREQ is a 32-bit twos complement number representing

the NCO frequency register.

f is the desired carrier frequency in hertz (Hz).

fCLK is the AD6655 ADC clock rate in hertz (Hz).

NCO SYNCHRONIZATION

The AD6655 NCOs within a single part or across multiple parts

can be synchronized using the external SYNC input. Bit 3 and

Bit 4 of Register 0x100 allow the NCO to be resynchronized on

every SYNC signal or only on the first SYNC signal after the

the programmed phase offset value.

PHASE OFFSET

The NCO phase offset register at Address 0x122 and

Address 0x123 adds a programmable offset to the phase

accumulator of the NCO. This 16-bit register is interpreted as

a 16-bit unsigned integer. A 0x00 in this register corresponds

to no offset, and a 0xFFFF corresponds to an offset of 359.995°.

Each bit represents a phase change of 0.005°. This register allows

multiple NCOs to be synchronized to produce outputs with

predictable phase differences. Use the following equation to

calculate the NCO phase offset value:

NCO_PHASE = 216 × PHASE/360

where:

NCO_PHASE is a decimal number equal to the 16-bit binary

number to be programmed at Register 0x122 and Register 0x123.

PHASE is the desired NCO phase in degrees.

NCO AMPLITUDE AND PHASE DITHER

The NCO block contains amplitude and phase dither to improve

the spurious performance. Amplitude dither improves perfor-

mance by randomizing the amplitude quantization errors within

the angular-to-Cartesian conversion of the NCO. This option

reduces spurs at the expense of a slightly raised noise floor. With

amplitude dither enabled, the NCO has an SNR of >93 dB and

an SFDR of >115 dB. With amplitude dither disabled, the SNR

is increased to >96 dB at the cost of SFDR performance, which

is reduced to 100 dB. The NCO amplitude dither is recommended

and is enabled by setting Bit 1 of Register 0x11D.

AD6655 Datasheet(PDF) 39 Page - Analog Devices

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