AD9864 datasheet(20/48 Pages) AD

20 / 48 page

Data Sheet

AD9864

Rev. A | Page 19 of 47

DON'T

CARE

R/W

tHI tLOW

tDS

tDH

tDV

tEZ

tCLK

Figure 30. 3-Wire SPI Read Operation Timing

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

DOUTB

R/W

tHI tLOW

tDS

tDH

tDV

tCLK

Figure 31. 4-Wire SPI Read Operation Timing

POWER-ON RESET

The SPI registers are automatically set to their default settings

upon power-up when the VDDD supply crosses a threshold. This

ensures that the AD9864 is in a known state and placed in standby

for minimal power consumption. In the unlikely event that the

SPI registers were not reset to their default settings, an equivalent

software reset by writing 0x99 to Register 0x3F can be used as the

first SPI write command to provide additional assurance.

SYNCHRONOUS SERIAL INTERFACE (SSI)

The AD9864 provides a high degree of programmability of its

SSI output data format, control signals, and timing parameters

to accommodate various digital interfaces. In a 3-wire digital

interface, the AD9864 provides a frame sync signal (FS), a clock

output (CLKOUT), and a serial data stream (DOUTA) signal to

the host device. In a 2-wire interface, the frame sync information

is embedded into the data stream, thus only CLKOUT and

DOUTA output signals are provided to the host device. The SSI

control registers are SSICRA, SSICRB, and SSIORD. Table 8 to

Table 13 show the bit fields associated with these registers.

The primary output of the AD9864 is the converted I and Q

demodulated signal available from the SSI port as a serial bit

stream contained within a frame. The output frame rate is equal

to the modulator clock frequency (fCLK) divided by the digital

filter’s decimation factor that is programmed in the Decimator

by a Q word, where each word is either 24 bits or 16 bits long

and is given MSB first in twos complement form. Two optional

bytes may also be included within the SSI frame following the Q

word. One byte contains the AGC attenuation and the other

byte contains both a count of modulator reset events and an

estimate of the received signal amplitude (relative to full scale of

the AD9864 ADC). Figure 32 illustrates the structure of the SSI

data frames in a number of SSI modes.

The two optional bytes are output if the EAGC bit of SSICRA is

set. The first byte contains the 8-bit attenuation setting (0 = no

attenuation, 255 = 24 dB of attenuation), whereas the second byte

contains a 2-bit reset field and 6-bit received signal strength

field. The reset field contains the number of modulator reset

events since the last report, saturating at 3. The received signal

strength (RSSI) field is a linear estimate of the signal strength at

the output of the first decimation stage; 60 corresponds to a

full-scale signal.

The two optional bytes follow the I and Q data as a 16-bit word

provided that the AAGC bit of SSICRA is not set. If the AAGC

bit is set, the two bytes follow the I and Q data in an alternating

fashion. In this alternate AGC data mode, the LSB of the byte

containing the AGC attenuation is a 0, whereas the LSB of the

byte containing reset and RSSI information is always a 1.

In a 2-wire interface, the embedded frame sync bit (EFS) within

the SSICRA register is set to 1. In this mode, the framing

information is embedded in the data stream, with each eight

bits of data surrounded by a start bit (low) and a stop bit (high),

and each frame ends with at least 10 high bits. FS remains either

low or three-stated (default), depending on the state of the SFST

bit. Other control bits can be used to invert the frame sync

(SFSI), to delay the frame sync pulse by one clock period

(SLFS), to invert the clock (SCKI), or to three-state the clock

(SCKT). Note that if EFS is set, SLFS is a don’t care bit.

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