ADF9010BCPZ datasheet(13/29 Pages) AD

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ADF9010

Rev. 0 | Page 12 of 28

CIRCUIT DESCRIPTION

Rx SECTION

DC OFFSET

CORRECTION

RxBBIP

RxBBIN

RxINIP

RxININ

PGA

SETTING

OVF

Figure 12. Rx Filter

The Rx section of the ADF9010 features programmable base-

band low-pass filters. These are used to amplify the desired Rx

signal from the demodulator while removing the unwanted

portion to ensure no antialiasing occurs in the Rx ADC.

These filters have a programmable gain stage, allowing gain to

be selected from 3 dB to 24 dB in steps of 3 dB. The bandwidth

of these filters is also programmable, allowing 3 dB cutoff fre-

quencies of 330 kHz, 880 kHz, and 1.76 MHz, along with a

bypass mode. The filters utilize a fourth-order Bessel transfer

function (see the Specifications section for more information).

If desired, the filter stage can be bypassed.

Additionally, a rising edge on the OVF pin reduces the gain of

the Rx amplifiers by 6 dB. This is to correct a potential overflow

of the input to the ADC.

Updating the Rx calibration latch with the calibration bit

enabled calibrates the filter to remove any dc offset. The

3 dB cutoff frequency (fC) of the filters is calibrated also.

LO SECTION

LO Reference Input Section

The LO input stage is shown in Figure 13. SW1 and SW2

are normally closed switches; SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

TO R COUNTER

REFIN

100kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

BUFFER

Figure 13. Reference Input Stage

R COUNTER

The 14-bit R counter allows the input clock frequency to be

divided down to produce the input clock to the phase frequency

detector (PFD). Division ratios from 1 to 8191 are allowed.

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide range of division ratios in the PLL

feedback counter. The counters are specified to work when

the prescaler output is 300 MHz or less.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler (see Figure 14), make it possible to generate large

divider ratios. The equation for N is as follows:

N = BP + A

where:

N is the overall divider ratio of the signal from the external

RF input.

P is the preset modulus of the dual-modulus prescaler.

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).

A is the preset divide ratio of the binary 5-bit swallow counter

(0 to 31).

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

13-BIT B

COUNTER

6-BIT A

COUNTER

TO PFD

N DIVIDER

MODULUS

CONTROL

N= BP + A

Figure 14. A and B Counters

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF input stage and divides it down

to a manageable frequency for the A and B CMOS counters.

The prescaler is programmable. The prescaler can be set in

software to 8/9, 16/17, or 32/33. For the ADF9010, however,

the 16/17 and 32/33 settings should be used. It is based on a

synchronous 4/5 core. A minimum divide ratio is possible for

fully contiguous output frequencies. This minimum is deter-

mined by P, the prescaler value, and is given by (P2 − P).

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