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AD2S1210CSTZ Datasheet(PDF) 33 Page - Analog Devices

Part # AD2S1210CSTZ
Description  Variable Resolution, 10-Bit to 16-Bit R/D Converter
PDF  37 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD2S1210CSTZ Datasheet(HTML) 33 Page - Analog Devices

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AD2S1210
Rev. A | Page 32 of 36
CIRCUIT DYNAMICS
LOOP RESPONSE MODEL
ERROR
(ACCELERATION)
–
θIN
θOUT
VELOCITY
k1 × k2
1 – z–1
1 – bz–1
1 – z–1
c
1 – az–1
c
Sin/Cos LOOKUP
Figure 38. RDC System Response Block Diagram
The RDC is a mixed-signal device that uses two ADCs to digitize
signals from the resolver and a Type II tracking loop to convert
these to digital position and velocity words.
The first gain stage consists of the ADC gain on the sine/cosine
inputs and the gain of the error signal into the first integrator.
The first integrator generates a signal proportional to velocity.
The compensation filter contains a pole and a zero that are used
to provide phase margin and reduce high frequency noise gain.
The second integrator is the same as the first and generates the
position output from the velocity signal. The sin/cos lookup has
unity gain. The values for the k1, k2, a, b, and c parameters are
outlined in Table 28.
The following equations outline the transfer functions of the
individual blocks as shown in Figure 38, which then combine to
form the complete RDC system loop response.
Integrator1 and Integrator2 transfer function
1
1
)
(
−
−
=
z
c
z
I
(10)
Compensation filter transfer function
1
1
1
1
)
(
−
−
−
−
=
bz
az
z
C
(11)
RDC open-loop transfer function
)
(
)
(
)
(
2
z
C
z
I
k2
k1
z
G
×
×
×
=
(12)
RDC closed-loop transfer function
)
(
1
)
(
)
(
z
G
z
G
z
H
+
=
(13)
The closed-loop magnitude and phase responses are that of a
second-order low-pass filter (see Figure 11 and Figure 12).
To convert G(z) into the s-plane, an inverse bilinear transforma-
tion is performed by substituting the following equation for z:
s
t
s
t
z
−
+
=
2
2
(14)
where t is the sampling period (1/4.096 MHz ≈ 244 ns).
Substitution yields the open-loop transfer function, G(s).
)
1
(
2
)
1
(
1
)
1
(
2
)
1
(
1
4
1
)
1
(
)
(
2
2
2
b
b
t
s
a
a
t
s
s
t
s
st
b
a
a
k2
k1
s
G
−
+
×
+
−
+
×
+
×
+
+
×
−
−
×
=
(15)
This transformation produces the best matching at low frequencies
(f < fSAMPLE). At such frequencies (within the closed-loop
bandwidth of the AD2S1210), the transfer function can be
simplified to
2
1
2
1
1
)
(
st
st
s
K
s
G
a
+
+
×
≅
(16)
where:
b
a
a
k2
k1
K
b
b
t
t
a
a
t
t
a
−
−
×
=
−
+
=
−
+
=
)
1
(
)
1
(
2
)
1
(
)
1
(
2
)
1
(
2
1
Solving for each value gives t1, t2, and Ka as outlined in Table 29.
Table 28. RDC System Response Parameters
Parameter
Description
10-bit resolution
12-bit resolution
14-bit resolution
16-bit resolution
k1 (nominal)
ADC gain
1.8/2.5
1.8/2.5
1.8/2.5
1.8/2.5
k2
Error gain
6 × 106 × 2
π
18 × 106 × 2
π
82 x 106 × 2
π
66 × 106 × 2
π
a
Compensator zero coefficient
8187/8192
4095/4096
8191/8192
32,767/32,768
b
Compensator pole coefficient
509/512
4085/4096
16,359/16,384
32,757/32,768
c
Integrator gain
1/1,024,000
1/4,096,000
1/16,384,000
1/65,536,000



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