2002 Oct 08

6

Philips Semiconductors

Product specification

HF full bridge driver IC

UBA2033

’Dead time’ can be increased by adding a resistor (for

slowly turning on the full bridge power FETs) and a diode

(for quickly turning off the full bridge power FETs) in

parallel, both in series with the gate drivers (see Fig.3).

Divider function

If pin DD = SGND, then the divider function is

enabled/present. If the divider function is present there is

no direct relation between the position of the bridge output

and the status of pin EXTDR.

Start-up delay

HV reaches the level of release power drive. At this

moment the gate drive voltage is equal to the voltage on

high side transistors. If this voltage is too low for sufficient

drive of the MOSFETs the release of the power drive can

be delayed via pin SU.

C between pins SU and SGND) can be used to make a

delay, or a control signal from a processor can be used.

Bridge disable

The bridge disable function can be used to switch off all the

MOSFETs as soon as the voltage on pin BD exceeds the

bridge disable voltage (1.29 V). The bridge disable

function overrules all the other states.

Table 1

Logic table; note 1

Note

1. X = don’t care

a) BD, SU and DD logic levels are with respect to SGND

c) GHL logic levels are with respect to SHL

d) GHR logic levels are with respect to SHR

e) GLL and GLR logic levels are with respect to PGND

f) If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the

pre-defined position pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW.

DEVICE

STATUS

INPUTS

OUTPUTS

BD

SU

DD

EXTDR

GHL

GHR

GLL

GLR

Start-up state

HIGH

X

X

X

LOW

LOW

LOW

LOW

LOW

X

X

X

LOW

LOW

HIGH

HIGH

Oscillation state

HIGH

X

X

X

LOW

LOW

LOW

LOW

LOW

LOW

X

X

LOW

LOW

HIGH

HIGH

LOW

HIGH

HIGH

HIGH

LOW

HIGH

HIGH

LOW

LOW

HIGH

LOW

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

LOW

LOW

HIGH

LOW-to-HIGH

HIGH

HIGH-to-LOW

LOW

HIGH

HIGH

LOW