VT6304 datasheet(7/21 Pages) ETC

7 / 21 page

VIA Technologies, Inc.

Preliminary VT6304

CNA

CNA is asserted high when none of the PHY ports are

connected to another active port. This circuit remains active

during the powerdown mode.

CMC

Programable Contender/Bus Manager Capable. It specifies in

the Self-ID packet that the node is capable of being a bus

manager.

44, 43, 42

PC[0-2]

Power

Class.

These

pins

are

used

set

the

three

POWER_CLASS bits in the Self-ID packet. They are used to

describe the power consumption and source characteristics of

the node. PC0, 1, 2 are reflected in the Self-ID packet bits 21,

22, 23, respectively.

TSI

Single Self ID packet. If port 4 is unused, i.e, the resistors and

capacitors for port 4 are not implemented, there is no need to

send the 2nd self ID packet, and the system can get benefit by

tying this pin to digital VDD to reduce self ID packet exchange

time.

TSO

Test pin. Tied to VT6304 digital VDD ring for normal

operations.

ONCT

On Chip Termination. If the capacitive isolation barrier is

implemented between the VT6304 and LLC, tie this pin to

VDD will utilize on chip resistors to replace on board 5K

Ohms resistors pair for LREQ, CTL[0:1] and D[0:7] at PHY

side. The resistors for LPS input at PHY side are also replaced

if this pin is tied to VDD. This pin has effects on on-chip

terminations only if ISO_ is tied to ground.

Power Down. A logic High on this pin turns off all internal

cicuitry except the connection detect circuits, which outputs

the CNA signal.

RESET_

I/NC

Reset (active low). The reset pin is connected to an internal 10K

ohm resistor and an external 0.1 uF capacitor is used for

internal reset generation at power-on. The pin can be left

unconnected to save the external capacitors, and then the reset

time after power-on ranges from 0.5 ms to 2 ms. This pin can

also be driven by an open-drain type driver.

38, 37

XI, XO

Crystal

Crystal Oscillator, 3.3V. These pins connect to a 24.576 MHz

parallel resonant fundamental mode crystal. The optimum

values for the external shnut capacitors are dependent on the

specifications of the cystal used. The resulting frequency

variation is +/- 100 ppm.

36, 35

XREXT,

GNDARE

I/O

Current setting resistor terminals. A resistor of 6.2 KOhm +/-

0.5% is required for internal operating currents generation.

Power Supply & Ground

88, 99, 13,

VDDARX

supply

Analog receiver power. A combination of high-frequency

decoupling capacitors near these pins are suggested. These

pins are seperated from digital power for noise prevention.

89, 100, 25,

GNDARX

supply

Analog receiver ground. These pins are tied together to the low-

impedance circuit board ground.

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