CY25823
Document #: 38-07579 Rev. *C
Page 2 of 12
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.The combined 7 bits slave address and
read/write bit form a complete block write (D4h) or block read
(D5h) command.
Pin Definitions
Pin No.
Name
Type
Description
1
CLKIN
Input
3.3V 14.131818-MHz single-ended clock input
2,3,4
S[3:1]
Input
Spread Spectrum configuration
5
PWRDWN
Input
3.3V LVTTL input for power-down active high, no pull-up or pull-down
6
REFOUT/SEL
I/O
Latched input during power-up, 1 (10K external pull-up) = 100 MHz or 0
(10K external pull-down) = 96 MHz. After power-up it becomes 14.31818-MHz
REFOUT clock.
7
SCLK
Input
SMBus-compatible SCLK
8SDATA
I/O
SMBus-compatible SDATA
9
VDD
3.3V
3.3V power supply for logic and outputs
10
VSS
Ground
Ground for logic and outputs
11
CLKOUT#
Output
0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output
12
CLKOUT
Output
0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output
13
VSSIREF
Ground
Current reference ground
14
IREF
Input
Typically a precision 475
Ω external resistor is connected between this
pin and VSSIREF to set IOUT (drive current) of CLKOUT differential
driver.
15
VSSA
Ground
Ground for PLL
16
VDDA
3.3V
3.3V power supply for PLL
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should
be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits (D4)
2:8
Slave address – 7 bits (D5)
9
Write = 0
9
Read = 0
10
Acknowledge from slave
10
Acknowledge from slave
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