TMS320VC5509APGE datasheet(21/144 Pages) TI

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Introduction

November 2002 − Revised January 2005

SPRS205D

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

BK‡

FUNCTION

I/O/Z†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

I/O/Z

EMIF asynchronous memory read enable or general-purpose IO8. This

pin serves in one of two functions: EMIF asynchronous memory read

enable (EMIF.ARE) or general-purpose IO8 (GPIO8). The initial state of

this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.ARE

O/Z

Active-low EMIF asynchronous memory read enable. EMIF.ARE is

selected when the Parallel Port Mode bit field of the External Bus Selection

EMIF.ARE

GPIO0 = 0:

Input,

GPIO8

I/O/Z

General-purpose IO8. GPIO8 is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO8

O/Z

EMIF asynchronous memory output enable or HPI interrupt output. This

pin serves in one of two functions: EMIF asynchronous memory output

enable (EMIF.AOE) or HPI interrupt output (HPI.HINT). The initial state of

this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.AOE

O/Z

Active-low asynchronous memory output enable. EMIF.AOE is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is 00 or 01.

EMIF.AOE

GPIO0 = 0:

Output,

HPI.HINT

O/Z

Active-low HPI interrupt output. HPI.HINT is selected when the Parallel

Port Mode bit field of the External Bus Selection Register is 10 or 11.

Output,

HPI.HINT

I/O/Z

EMIF asynchronous memory write enable or HPI read/write. This pin

serves in one of two functions: EMIF asynchronous memory write enable

(EMIF.AWE) or HPI read/write (HPI.HR/W). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.AWE

O/Z

Active-low EMIF asynchronous memory write enable. EMIF.AWE is

selected when the Parallel Port Mode bit field of the External Bus Selection

EMIF.AWE

GPIO0 = 0:

Input,

HPI.HR/W

HPI read/write. HPI.HR/W is selected when the Parallel Port Mode bit field

of the External Bus Selection Register is 10 or 11. HPI.HR/W controls the

direction of the HPI transfer.

Input,

HPI.HR/W

I/O/Z

EMIF data ready input or HPI ready output. This pin serves in one of two

functions: EMIF data ready input (EMIF.ARDY) or HPI ready output

(HPI.HRDY). The initial state of this pin depends on the GPIO0 pin. See

Section 3.5.1 for more information.

GPIO0 = 1:

Input,

EMIF.ARDY

EMIF data ready input. Used to insert wait states for slow memories.

EMIF.ARDY is selected when the Parallel Port Mode bit field of the

External Bus Selection Register is 00 or 01.

EMIF.ARDY

GPIO0 = 0:

Output,

HPI.HRDY

HPI ready output. HPI.HRDY is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10 or 11.

Output,

HPI.HRDY

† I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡ BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

TMS320VC5509APGE Datasheet(PDF) 21 Page - Texas Instruments

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