MT9D115D00STCK25AC1-200 datasheet(3/48 Pages) ONSEMI

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MT9D115

www.onsemi.com

TYPICAL CONNECTION

1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.

2. If a MIPI Interface is not required, the following pads must be left floating: DOUT_P, DOUT_N, CLK_P, and CLK_N.

3. The general purpose input/output (GPIO) pads can serve multiple features that can be reconfigured. The function and direction will vary

by applications.

4. Only one of the output modes (serial or parallel) can be used at any time.

5. ON Semiconductor recommends a resistor value of 1.5 k

W to VDD_IO for the two-wire serial interface RPULL-UP; however, greater values

may be used for slower transmission speed.

6. VAA and VAA_PIX may be tied together. Although separate decoupling capacitors are recommended for VAA and VAA_PIX, decoupling

capacitors can be shared if one would like to reduce module size.

7. VPP is the one-time programmable memory (OTPM) programming voltage and should be left floating during normal operation.

8. 1.8 V supply shared by MIPI interface and VDD to reduce number of decoupling caps, hence, module size. VDDIO_TX must be connected

to a 1.8 V power supply source even though MIPI interface is not used.

9. ON Semiconductor recommends that 0.1

mF and 1 mF decoupling capacitors for each power supply are mounted as close as possible to

the pad and that a 10

mF capacitor be placed nearby off-module. Actual values and results may vary depending on layout and design

considerations. Please follow ON Semiconductor’s recommended capacitor Recommendations.

10. VDD_PLL and VAA can share the same power source in which case GND_PLL must be connected to GND.

11. Internal pull-up in RESET_BAR pin and can be left floating when not connected.

Figure 2. Typical Configuration (Connection)

I/O

Power

AGND

SCLK

SDATA

VDD_IO

Notes:

PIXCLK

VDDIO_TX/VDD

VAA_PIX/

VDD_PLL/

VAA

DGND

GPIO[3:0]3

EXTCLK

RESET_BAR

SADDR

Analog

Power

VAA_PIX6

LINE_VALID

FRAME_VALID

DOUT[7:0]

CLK_N

CLK_P

Parallel

Camera

Port

Serial

Camera

Port2

OR4

RPULL-Up5

Slave

Two-wire

Serial

Interface

Active LOW Reset

External Clock In

(6−54 MHz)

General Purpose

I/Os (FLASH,

OE_BAR,

DOUT_LSB[1:0])

STANDBY

Standby Mode

GND_IO

GND_PLL

VAA6

DOUT_N

DOUT_P

Digital

Core

Power

VDD

PLL

Power

VDD_PLL

MIPI

Power

VDDIO_TX8

VPP7

0.1

MT9D115D00STCK25AC1-200 Datasheet(PDF) 3 Page - ON Semiconductor

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