AD7984 datasheet(13/25 Pages) AD

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AD7984

Data Sheet

THEORY OF OPERATION

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7984 is a fast, low power, single-supply, precise, 18-bit

ADC using a successive approximation architecture and is

capable of converting 1,330,000 samples per second (1.33 MSPS).

The AD7984 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple multiplexed channel applications.

The AD7984 can be interfaced to any 1.8 V to 5 V digital logic

family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP

that allows space savings and flexible configurations.

It is pin-for-pin-compatible with the 18-bit AD7982.

CONVERTER OPERATION

The AD7984 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 18 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via SW+ and

SW−. All independent switches are connected to the analog

inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. When the acquisition phase is complete and the CNV

input goes high, a conversion phase is initiated. When the

conversion phase begins, SW+ and SW− are opened first. The

two capacitor arrays are then disconnected from the inputs and

connected to the GND input. Therefore, the differential voltage

between the inputs IN+ and IN− captured at the end of the

acquisition phase is applied to the comparator inputs, causing

the comparator to become unbalanced. By switching each

element of the capacitor array between GND and REF, the

comparator input varies by binary-weighted voltage steps

(VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition. After the completion of this process,

the part returns to the acquisition phase, and the control logic

generates the ADC output code and a busy signal indicator.

Because the AD7984 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

65,536C

131,072C

LSB

SW+

MSB

LSB

SW–

MSB

65,536C

131,072C

IN+

REF

GND

IN–

Rev. B | Page 12 of 24

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