AD7623ASTZ datasheet(16/29 Pages) AD

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AD7623

Rev. 0 | Page 15 of 28

THEORY OF OPERATION

SW+

COMP

SW–

IN+

REF

REFGND

LSB

MSB

32,768C 16,384C

SWITCHES

CONTROL

LOGIC

BUSY

OUTPUT

CODE

CNVST

IN–

32,768C 16,384C

LSB

MSB

AGND

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7623 is a very fast, low power, single-supply, precise,

16-bit analog-to-digital converter (ADC) using successive

approximation architecture. The AD7623 is capable of

converting 1,330,000 samples per second (1.33 MSPS).

The AD7623 provides the user with an on-chip track-and-hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7623 can be operated from a single 2.5 V supply and

be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It

is housed in 48-lead LQFP or tiny LFCSP packages that

combine space savings with flexibility, allowing the AD7623

to be configured as either a serial or parallel interface. The

AD7623 is pin-to-pin-compatible with, and a speed upgrade

of, the AD7677.

CONVERTER OPERATION

The AD7623 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on IN+ and IN− inputs. A conversion

phase is initiated once the acquisition phase is complete and the

CNVST input goes low. When the conversion phase begins,

SW+ and SW− are opened first. The two capacitor arrays are

then disconnected from the inputs and connected to the

REFGND input. Therefore, the differential voltage between the

inputs (IN+ and IN−) captured at the end of the acquisition

phase is applied to the comparator inputs, causing the

comparator to become unbalanced. By switching each element

of the capacitor array between REFGND and REF, the

comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4 through VREF/65536). The control logic toggles

these switches, starting with the MSB first, in order to bring the

comparator back into a balanced condition.

After the completion of this process, the control logic generates

the ADC output code and brings BUSY output low.

The AD7623 automatically powers down circuits after

conversion, making the AD7623 ideal for battery-powered

applications.

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