AD7641BSTZ datasheet(22/29 Pages) AD

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AD7641

Rev. 0 | Page 21 of 28

INTERFACES

DIGITAL INTERFACE

PARALLEL INTERFACE

The AD7641 has a versatile digital interface that can be set up

as either a serial or a parallel interface with the host system. The

serial interface is multiplexed on the parallel data bus. The AD7641

digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic

with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic

high output voltage. In most applications, the OVDD supply pin

of the AD7641 is connected to the host system interface 2.5 V

or 3.3 V digital supply. By using the D0/OB/

The AD7641 is configured to use the parallel interface for an

18-bit, 16-bit, or 8-bit bus width according to Table 7.

Master Parallel Interface

2C input pin, either

twos complement or straight binary coding can be used.

The two signals CS and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7641 in

multicircuit applications and is held low in a single AD7641

design. RD is generally used to enable the conversion result on

the data bus.

RESET

The RESET input is used to reset the AD7641 and generate a

fast initialization. A rising edge on RESET aborts the current

conversion (if any) and tristates the data bus. The falling edge of

RESET clears the data bus and engages the initialization process

indicated by pulsing BUSY high. Conversions can take place

after the falling edge of BUSY. Refer to Figure 30 for the RESET

timing details.

RESET

DATA

BUSY

CNVST

t38

t39

Figure 30. RESET Timing

Data can be continuously read by tying CS

and

low, thus

requiring minimal microprocessor connections. However, in

this mode, the data bus is always driven and cannot be used in

shared bus applications, unless the device is held in RESET.

Figure 31 details the timing for this mode.

BUSY

DATA

BUS

PREVIOUS CONVERSION DATA

NEW DATA

CNVST

CS = RD = 0

t10

t11

Figure 31. Master Parallel Data Timing for Reading (Continuous Read)

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after

each conversion, which is during the next acquisition phase, or

during the following conversion, as shown in Figure 32 and

Figure 33, respectively. When the data is read during the

conversion, it is recommended that it is read-only during the

first half of the conversion phase. This avoids any potential

feedthrough between voltage transients on the digital interface

and the most critical analog conversion circuitry.

CURRENT

CONVERSION

t13

t12

BUSY

DATA

BUS

Figure 32. Slave Parallel Data Timing for Reading (Read After Convert)

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