MN85571AC

4

SDD00023AEM

s Internal Resource Mapping (continued)

2. Indirect addressing resources (registers and initial load memory)

These internal resources are accessed by storing the address of the indirect addressing resource in the INADR0

indirect access address register and reading or writing the INDAT0 indirect access data register. Other than the regis-

ters used for communication with the external host and the SRISC, these resources can only be accessed in the slave

state. While these resources have a structure that consists of 16 bits per address, indirect addressing access writes must

be performed in 32-bit units. Tables 2 and 3 show the address maps.

Table 2. Indirect Addressing Resources Address Map Overview

1

Description

$0000

− $01FF

Communication registers, parameter registers, and other registers

$0200

− $03FF

Video input intensity conversion data memory (ITDM) A: 256 words

$0400

− $05FF

Video input intensity conversion data memory (ITDM) A: 256 words

$0600

− $0FFF

Reserved

$1000

− $17FF

Video encoding block RISC data memory (VDM): 1K words

$1800

− $3FFF

Reserved

$4000

− $7FFF

Video encoding block RISC instruction memory (VIRAM): 8K words

× 32 bits

$8000

− $8FFF

Reserved

$9000

− $9FFF

Multiplexing block RISC data memory (SDM): 2K words

$A000

− $CFFF

Multiplexing block RISC instruction memory (SIRAM): 6K words × 24 bits 24 bits

$D000

− $FFFF

Reserved

Note) *1: The notation indir adr indicates the value stored in the INADR0 indirect access address register when

accessing an indirect addressing resource.

*2: Data only exists at even addresses.

Table 3. Indirect Addressing Resources (Registers) Address Map

Description

Name

Run/Hold

Slave

$0000

− $000F

External host/SRIC communication register

hifreg

q

×

$0010

− $0013

Reserved

××

$0014

Video input block parameter register

vifreg

×

W

$0015

− $001F

Reserved

××

$0020

DMA data I/O block parameter register

difreg

×

W

$0021

Reserved

××

$0022

− $0025

Code output block parameter register

cifreg

×

W

$0026

− $01FF

Reserved

××

Note) 1. *: The notation indir adr indicates the value stored in the INADR0 indirect access address register when

accessing an indirect addressing resource.

2. q: Both read and write access allowed. W: Write access allowed (Cannot be read.)

×: No access is allowed.

Chip operation is not guaranteed if registers for which access is only allowed in the slave state are

accessed in either the run or hold states.

Chip operation is not guaranteed if areas indicated as reserved are accessed.