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ACE25AC512GFMLTH Datasheet(PDF) 3 Page - ACE Technology Co., LTD. |
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ACE25AC512GFMLTH Datasheet(HTML) 3 Page - ACE Technology Co., LTD. |
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3 / 23 page ![]() ACE25AC512G SPI NOR FLASH VER 1.1 3 Block Diagram Uniform Block Sector Architecture ACE25AC512G 64K Bytes Block Sector Architecture Block Sector Address range 0 15 00F000H 00FFFFH …… …… …… 8 008000H 008FFFH 7 007000H 007FFFH …… …… …… 0 000000H 000FFFH Device Operation The ACE25AC512G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. |
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