8-283
RF2495
Rev A4 030220
Pin
Function
Description
Interface Schematic
1VCC1
Supply voltage for the LNA, bias circuits, and control logic. External RF
bypassing is required. The trace length between the pin and the bypass
capacitors should be minimized. The ground side of the bypass capaci-
tors should connect immediately to ground plane.
2LNA_IN
RF Input pin. This pin is internally matched for optimum noise figure
from a 50
Ω source. This pin is internally DC-biased and, if connected
to a device with DC present, should be blocked with a capacitor suit-
able for the frequency of operation.
3GND2
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
4GND1
Ground connection for the LNA circuits. For best performance, keep
traces physically short and connect immediately to ground plane.
See pin 2.
5
ATTN
Attenuation pin. A logic high reduces LNA gain by 15dB.
6LNA OUT
LNA Output pin. This pin requires a connection to VCC through an
inductor.
7SOURCE
Connection to source of MOSFET transistor used as mixer. Drain and
source are symmetric.
8DRAIN
Connection to drain of MOSFET transistor used as mixer.
See pin 7.
9GATE
Connection to gate of MOSFET transistor used as mixer. Internally
DC-biased. Use DC-blocking capacitor.
See pin 7.
10
PD
Power control. A logic “low” turns the part off. A logic “high” (>1.6V)
turns the part on.
ESD
This diode structure is used to provide electrostatic discharge protec-
tion to 3kV using the Human body model. The following pins are pro-
tected: 1, 3, 5, 9, 10.
GND1
LNA IN
VBIAS
ATTN
GND2
V
CC
LNA OUT
GATE
DRAIN
SOURCE
PD
GND2
V
CC
V
CC
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