| Manufacturer | Part # | Datasheet | Description |
STMicroelectronics |
STM32WL
|
329Kb/2P
|
The world?셲 first SoC enabling LoRa짰, (G)FSK, (G)MSK, BPSK
|
|
STM32WL54CC
|
3Mb/147P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
July 2021
|
|
STM32WL54CCI6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI6XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI6XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI7TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI7TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI7XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCI7XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU6XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU6XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU7TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU7TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU7XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCU7XXX
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCY6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
|
STM32WL54CCY6TR
|
2Mb/145P
|
Multiprotocol LPWAN dual core 32-bit Arm짰 Cortex짰-M4/M0+ LoRa짰, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
November 2020 Rev 1
|
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