Description
The TC518128B is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The
TC518128B operates from a single 5V power supply. Refreshing is supported by a refresh (RFSH) input which enables two types of
refreshing - auto refresh and self refresh. The TC518128B features a static RAM-like interface with a write cycle in which the input
data is written into the memory cell at the rising edge of RW thus simplifying the microprocessor interface.
The TC518128B is pin-compatible with the 1M bit CMOS static RAM JEDEC standard and is available in a 32-pin, 0.6 inch and
0.3 inch width plastic DIP, a small outline plastic flat package, and a 32-pin thin small outline plastic package (forward type).

Features
• Organization: 131,072 words x 8 bits
• Single 5V power supply
• Fast access time
ICEA CE Access Time
toEA OE Access Time
tRc Cycle Time
Power Dissipation
Self Refresh Current
TC518128B Family
-70
-80
-10
70ns
80ns
100ns
25ns
30ns
40ns
115ns
130ns
160ns
385mW 330mW 275mW
200μA (L version)
50μA (LL version)
Auto refresh is supported by an internal refresh address
counter
TC518128BPL
- TC518128BFL
- TC518128BSPL
- TC518128BFWL
- TC518128BFTL
• Self refresh is supported by an internal timer
• Inputs and outputs TTL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Pin compatible: 1M SRAM (JEDEC)
• Package
: DIP32-P-600
: SOP32-P-450
: DIP32-P-300
: SOP32-P-525
: TSOP32-P-0820