DESCRIPTION
The TC558128BJ/BFT is a 1,048,576-bit high-speed static random access memory (SRAM) organized as
131,072 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high
speed, it operates from a single 5 V power supply. There are two control inputs. Chip enable (CE) can be used
to place the device in a low-power mode, and output enable (OE) provides fast memory access. This device is
well suited to cache memory applications where high-speed access and high-speed storage are required. All
inputs and outputs are directly TTL compatible. The TC558128BJ/BFT is available in a plastic 32-pin SOJ
(400 mil width) and TSOP packages for high density surface assembly.

FEATURES
• Fast access time (the following are maximum values)
TC558128BJ/BFT-10: 10 ns
• Low-power dissipation
(the following are maximum values)
Cycle Time
10 12 15 20 25 ns
Operation (max) 210 190 170 140 130 mA
Standby: 1 mA (both devices)
Single power supply voltage of 5 V ± 5%.
• Fully static operation
• All inputs and outputs are TTL compatible
• Output buffer control using OE
● Package:
SOJ32-P-400-1.27A (BJ)
(Weight: 1.22 g typ)
TSOPII 32-P-400-0.80C (BFT) (Weight: 0.34 g typ)