Description
The TC5589P/J is a 73,728 bit high speed CMOS static random access memory organized as 8,192 words by 9 bits and operated
from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.
The TC5589P/J features low power dissipation when the device is deselected using chip enable (CE1, CE2) and has an output
enable input (OE) for fast memory access. Also, the device power between memory accesses is reduced by an automatic power
down circuit.
The TC5589P/J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and
outputs are TTL compatible.
The TC5589P/J is available in a 300mil width, 28-pin DIP and SOJ suitable for high density surface assembly.

Features
• Fast access time
- TC5589P/J-15
- TC5589P/J-20
- TC5589P/J-25
- TC5589P/J-35
15ns (max.)
20ns (max.)
25ns (max.)
35ns (max.)
• Low power dissipation
- Operation:
- TC5589P/J-15
- TC5589P/J-20
- TC5589P/J-25
- TC5589P/J-35
- Standby:
135mA (max.)
115mA (max.)
115mA (max.)
115mA (max.)
1mA (max.)
Single 5V power supply: 5V±10%
• Fully static operation
• Inputs and outputs TTL compatible
Output buffer control: OE
• Package:
- TC5589P: DIP28-P-300B
- TC5589J: SOJ28-P-300A